(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to the fabrication of a dual bit flash memory having increased bit density over a single bit flash memory, but without the disadvantages of multi-level cell technology.
(2) Description of the Prior Art
Improvements in Flash memory devices are sought continuously. One area of desired improvement is in bit density. One way to increase bit density in flash memory is to adopt a multi-level cell technology. The multi-level cells store fractional levels of charge within a cell to provide increased data storage capability. This means that each of the levels requires a precisely metered number of electrons to be stored in the floating gate and each of the levels has its own threshold voltage (Vt) margin. As a result, program operation needs to be performed carefully and is inherently slow in comparison with conventional single bit technology program operation. Furthermore, multi-level cell devices generally much use higher operating voltages to ensure a Vt window wide enough to accommodate all levels. The associated high fields result in oxide wear-out and limit the endurance of the device. It is desired to increase bit density without resorting to multi-level cell technology.
U.S. Pat. No. 6,462,375 to Wu et al discloses two floating gates having a shared select gate/control gate therebetween. U.S. Pat. Nos. 6,151,248, 6,344,993 and 6,266,278 to Harari et al show floating gates on the sidewalls of a select gate. U.S. Pat. Nos. 6,133,098, 6,366,500, and 6,359,807 to Ogura et al describe two floating gates on the sidewalls of a select gate wherein a control gate separates each set of select gate/floating gates.